1. Field of the Disclosure
Generally, the present disclosure relates to semiconductor devices and, in particular, to techniques for controlling plasma antenna effects during any plasma treatments to be performed during the manufacturing of semiconductor devices.
2. Description of the Related Art
Manufacturing semiconductor products, such as integrated circuits, individual components, such as transistors, diodes and the like, may typically involve a plurality of process steps performed on the basis of an appropriate carrier or substrate material. The substrate material, frequently provided in the form of an appropriate semiconductor material, such as silicon and the like, is processed by patterning specific device-related structures, which typically involves the deposition of one or more appropriate material layers, providing a respective mask layer so as to define the lateral size and shape of the respective features, followed by a patterning process, such as an etch process, in order to remove unwanted material portions of the previously deposited one or more material layers. In this manner, layer-for-layer, further components of a specific circuit element may be formed, wherein precise alignment to the previously patterned layers is required.
During the early phase of semiconductor production, in particular, the patterning of respective material layers on the basis of appropriately configured masking layers was accomplished on the basis of wet chemical etch recipes. Based on these etch recipes, a precise transfer of the lateral dimensions of a respective mask layer into the deeper lying one or more material layers to be patterned was typically a difficult process, since a certain amount of under-etching had to be taken into consideration due to the wet chemical nature of the patterning process. Although, in view of these etch-related difficulties, anisotropic etch techniques have been developed, in which very different etch rates are obtained depending on crystallographic orientations of crystal planes, it still appeared to be very difficult to further reduce the lateral dimensions of circuit patterns, since such anisotropic etch techniques are effective only for crystalline base materials, while other materials, such as oxide materials, nitride materials and the like, still exhibited a significant amount of under-etching, thereby introducing significant process variations into the overall process flow.
Upon introducing plasma-assisted process techniques, significant progress was made in the field of semiconductor fabrication, since from that point on, many processes, in particular, etch processes, could be performed on the basis of a highly directional behavior. That is, by introducing plasma techniques in which certain species in the plasma ambient may be ionized and appropriately accelerated to the substrate material to be treated, thereby obtaining a high degree of directionality of the respective accelerated particles, even the chemical effect of a plurality of etch species could be provided with a well-defined directionality, thereby providing “anisotropic” etch characteristics for respective plasma-assisted removal processes, without being restricted to crystallographic orientations of crystalline materials. The potential for implementing plasma-assisted process techniques has been widely taken advantage of, since, for instance, from that point on, it was possible to transfer respective contours of mask layers into the lower-lying material layers with a high degree of fidelity, while avoiding, or at least significantly reducing, any under-etching effects.
Moreover, plasma-assisted processes have also been introduced into other concepts, such as deposition processes, in which the reactive behavior of certain components can be increased without requiring specific high temperatures, which would otherwise be necessary for initiating a desired chemical reaction. In still other cases, plasma treatments for incorporating certain species, adjusting surface characteristics of specific material layers, and the like, are also frequently applied in sophisticated manufacturing strategies for forming semiconductor devices.
When using a plasma ambient for treating a semiconductor substrate, however, certain side effects are involved, since, depending on the materials exposed to the plasma ambient, the more or less continuous “bombardment” of charged particles may affect exposed surface areas or even underlying material components. That is, certain surface areas may act as “antenna” on which charge may accumulate due to the continuous “bombardment” of charged particles of the plasma ambient. Therefore, the respective charge may have to be discharged in order to prevent undue voltages from building up within the substrate to be treated. For example, when patterning a gate electrode structure for a field effect transistor, a relatively thin gate dielectric material, which may have a thickness of several nanometers and even less in sophisticated devices, may have to be formed in combination with appropriate electrode materials, such as polysilicon and the like. Since a corresponding patterning process requires precise transfer of the mask dimensions into the underlying material layers, respective plasma-assisted etch recipes have to be applied, thereby also contributing to respective adverse side effects of the plasma ambient. During certain phases of the overall patterning process, charge may accumulate in the respective antenna, i.e., for instance, the gate electrode material, and may possibly lead to voltages that may exceed the breakdown voltage of the sensitive gate dielectric materials. Therefore, respective discharge paths may have to be provided for the charge during a plasma treatment in order to reliably restrict the accumulation of charges to a non-critical level. For example, the substrate material may be connected to a corresponding electrode assembly of the plasma process tool in order to discharge unwanted charges, which, in turn, may be discharged from respective critical surface areas into the substrate material. With the introduction of ever-decreasing feature sizes and more complex structures and, in particular, the incorporation of device architectures resulting in substantially vertically isolated device areas, such as semiconductor- or silicon-on-insulator (SOI) configurations, it becomes increasingly difficult to provide appropriate discharge paths for maintaining parasitic voltages at a non-critical level during plasma treatments.
For these reasons, circuit designers have been forced to intentionally add respective discharge structures, such as substrate diodes in combination with appropriate conductive paths, which may connect to critical device features, such as gate electrode structures, drain and source regions and, in particular, to SOI transistors, and the like, so as to provide efficient discharge mechanisms during one or more plasma treatments. Consequently, significant efforts have been made in order to appropriately implement corresponding diode structures, also typically referred to as antenna diodes, into the overall design and to provide appropriate conductive paths that are available during the various stages of the overall manufacturing processes in order to avoid or at least significantly reduce the probability of plasma-induced damage of sensitive device areas.
In recent developments, planar transistor configurations have been introduced with critical dimensions in the range of 30 nm and significantly less, thereby providing the potential for implementing more and more functions into a single integrated circuit. Therefore, radio frequency (RF) devices and analog devices may have to be frequently provided in combination with digital control circuitry, thereby contributing even further to the overall complexity of respective integrated circuits. It appears that circuit elements for RF circuits or circuit portions and analog circuits or circuit portions may particularly exhibit an even further increased sensitivity to the effects of plasma-induced charge generation and exposed surface areas, thereby requiring an even further increased density of respective antenna diodes and corresponding conductive paths.
Although such protective structures have been successfully implemented in modern circuits designs, it appears, nevertheless, that such additional protective structures, which may not have any function during the actual operation of a corresponding semiconductor device, may negatively affect the operational behavior, since such protective structures, such as antenna diodes and the like, are typically associated with additional capacitance and also contribute to increased leakage currents, which may, therefore, have to be taken into consideration when designing and evaluating performance of any such complex semiconductor devices. In particular, in sophisticated fully depleted SOI semiconductor devices, it appears that superior protection of source and drain regions, as well as the gate electrode, may be required, since the source and drain regions, in particular, may no longer act as a direct diode to the substrate due to the SOI architecture. The added parasitic capacitance and leakage contribute to reduced device performance, in particular, in RF and analog circuit portions, as discussed above, and increasingly complicated design may also be necessary for bipolar operation in such sophisticated SOI devices, thereby contributing to increased manufacturing costs and reduced performance. Moreover, upon further increasing the overall complexity of the circuit designs and reduction of critical dimensions, the respective antenna effects during the various plasma treatments may not be precisely predicted, or measurement thereof may be very complex, thereby also contributing to reduced manufacturing efficiency. This, in turn, also results in increased cost due to reduced production yield.
In view of the situation described above, the present disclosure, therefore, relates to semiconductor devices, manufacturing techniques and evaluation strategies in which, generally, adverse effects of plasma treatments on semiconductor devices may be addressed so as to avoid or at least reduce the effects of one or more of the problems identified above.